In conventional integrated circuits, as shown in FIG. 1, there are provided a parallel data input port PI and a parallel output port PO, and further provided a serial interface SIF for performing serial communication with a microcomputer or other integrated circuits. In this serial interface SIF, there are provided a serial input terminal SI for data, a serial output terminal SO for data, a clock terminal SCK for communication, and a chip selection terminal CS for selecting a chip to communicate with.
In practice, an integrated circuit has some terminals used for both inputting and outputting data. Therefore, input terminals, output terminals, and terminals for both inputting and outputting data should be called an input/output port as a whole. However, in this specification, the terms of input port and output port are used for simplicity. Furthermore, a parallel input port PI and parallel output port PO are not always arranged in such a regular form, besides some integrated circuits do not have a parallel input port. However, arrangement in regular form is used in Figures for simplicity.
To connect a plurality of integrated circuits having such structure shown in FIG. 2, a parallel output port POA of a first integrated circuit ICA is connected to a parallel input port PIB of a second integrated circuit ICB, and furthermore, corresponding a serial input terminal SI, a serial output terminal SO and a clock terminal SCK of a microcomputer 9 are connected to integrated circuits ICA and ICB in common. Each chip selection terminals CS of integrated circuits ICA and ICB is individually connected to a microcomputer 9 for control, so that time sharing communication with a chip selected by the chip selection terminal CS is performed.
To perform data transmission or reception between these connected integrated circuits, it is required to test whether or not every parallel input port PI and parallel output port PO of all integrated circuits are surely connected. As integrated circuits are mounted at higher density on a limited area of circuit board, difficulty becomes more serious in surely testing a state of connection due to more complicated connection.
One of the methods proposed to solve the above problems is a testing method called boundary scan (hereafter referred to simply as B/S) method (IEEE Std, 1149.1-1990, issue May 21, 1990). In this method, as shown in FIG. 3, this type of integrated circuit IC11 has a testing interface TIF for B/S in addition to a parallel data input port PI, a parallel output port PO, and a serial interface SIF for serial communication. Provided that same as drawings in prior art shall not apply to designation symbols of application drawings in the present invention.
This testing interface TIF comprises a testing serial input terminal TSI for inputting testing data in serial form from the outside, a testing serial output terminal TSO for outputting the input testing data in serial form, a testing clock input terminal TCK for inputting a clock signal for use in processing of the testing data, and a testing mode selection terminal TMS for inputting a command which sets the integrated circuit IC11 to a testing mode.
As shown in FIG. 4, in this integrated circuit IC11, between the parallel input port PI and a function logic circuit FLG for performing predetermined data processing, there are provided boundary-scan cells (shortened form of B/S cell) BC1 to BC4 which correspond respectively to input terminals PI1 to PI4 of the parallel input port PI. This integrated circuit has an input/output port in a 4-bit form. The parallel input port PI consists of four input terminals PI1 to PI4. Each of these input terminals PI1 to PI4 is individually connected to each of B/S cells BC1 to BC4.
Furthermore, between the parallel output port PO and the function logic circuit FLG for performing predetermined data processing, there are provided B/S cells BC 5 to BC8 which correspond respectively to output terminals PO5 to PO8 of the parallel output port PO.
Each of B/S cells BC1 to BC8 has a switching circuit and a latch circuit so that it inputs and holds data, and transfers the data on the basis of a clock. Other features of structure of B/S cells are disclosed in the literature described above.
For simplicity, the testing clock input terminal TCK and the testing mode selection terminal TMS are not shown in FIG. 4.
The integrated circuit IC11 having the structure described above performs operation comprising steps of:
(1) transferring 4-bit serial data, being input into the testing signal input terminal TSI, to B/S cells BC5 to BC8 via B/S cells BC1 to BC4, then outputting the data from the testing serial output terminal TSO;
(2) storing temporarily 4-bit data, being input in parallel form from the input terminals PI1 to PI4, in B/S cells BC1 to BC4, then transferring the stored data to B/S cells BC5 to BC8, furthermore outputting the data in serial form via the testing serial output terminal TSO; and
(3) transferring 4-bit serial data, input into the testing serial input terminal TSI, to B/S cells BC5 to BC8 via B/S cells BC1 to BC4, then outputting the data in parallel form from the corresponding output terminals PO5 to PO8.
The integrated circuit IC11 having a testing interface TIF and B/S cells BC1 to BC8, and integrated circuits IC12, IC13 and IC14 having similar structure are connected in such a manner shown in FIG. 5. 4-bit serial testing data TD is input into the testing serial input terminal TSI of the first integrated circuit IC11. This input testing data TD is transferred to the B/S cells BC5 to BC8 via the B/S cells BC1 to BC4 shown in FIG. 4, and then is output to the parallel input port PI of the second integrated circuit IC12.
The testing data TD, input into the parallel input port PI of the second integrated circuit IC12, is stored in B/S cells (similar to the B/S cells BC1 to BC4 in FIG. 4) provided to correspond to the parallel input port PI of the second integrated circuit IC12, and then it is transferred to the B/S cells (similar to the B/S cells BC5 to BC8 in FIG. 4) corresponding to the parallel output PO of the second integrated circuit IC12, and finally it is output from the testing serial output terminal TSO. Similarly, after that, in integrated circuits IC13 and IC14, the testing data is input and output via testing serial input terminals TS1 and via testing serial output terminals TSO of these integrated circuits.
In this way, testing data TD is outputted via the parallel output port PI of the integrated circuit IC11 and via the parallel input port PO of the integrated circuit IC12. When "1111" is input, for example, as testing data TD, if there exists any disconnection or defective connection in any of parallel signal lines between the parallel output port PO of the integrated circuit IC11 and the parallel input port PI of the integrated circuit IC12, just portions of the data corresponding to the failure become "0" in the serial data output from the testing serial output terminal TSO of the second integrated circuit IC12. Thus, for example, "1011" or such a kind of data will be output.
Therefore, a state of connection between the first integrated circuit IC11 and the second integrated circuit IC12 can be tested based on the above output data.
For simplicity of explanation, a case in which connection is made in regular form is described here, while the integrated circuit IC11, in practice, might be also connected to the integrated circuit IC13, or the output of the integrated circuit IC12 might be input into the integrated circuit IC11.
However, the testing interface TIF, which is provided in the above integrated circuit for inputting or outputting testing data, leads to complexity in the structure.